從感測到智慧運算，讓晶片以更少能源回應真實世界。探索三個研究領域，或展開各項技術成果。From sensing to intelligent computation, our chips respond to the real world with less energy. Explore three research areas and the technologies behind them.
研究成果總覽Research Record Overview
研究團隊以低功耗類比與混合訊號積體電路設計為研究核心，結合可編程感測介面、記憶體內運算及能源管理技術，逐步由電路元件創新發展至智慧感測系統整合。自2011年於國立臺灣科技大學任教，至2025年8月轉任國立陽明交通大學電機工程學系教授，研究持續圍繞如何在有限能源與硬體資源下，可靠地擷取訊號、即時完成判讀，並支援後續的系統反應。研究團隊於2023年榮獲國立臺灣科技大學頒發之『111學年度研究優良獎(產學類)』，兩年後於2025年榮獲國立臺灣科技大學頒發之『113學年度傑出研究奬』，並於2026年榮獲國科會『2026年未來科技獎』。Research centers on low-power analog and mixed-signal IC design, connecting programmable sensing interfaces, in-memory computing and energy management. Work has progressed from circuit innovations to integrated smart-sensing systems. Since joining NTUST in 2011 and moving to NYCU in August 2025, the central question has been how to acquire signals reliably, interpret them in real time and support system responses under limited energy and hardware resources. Recognitions include NTUST’s academic-year 111 Industry–Academia Research Excellence Award in 2023, academic-year 113 Outstanding Research Award in 2025, and the 2026 Future Tech Award.
研究歷程與計畫概況Research background & project overview
依機器人與智慧控制、精準智慧醫療、電源管理與綠能三項領域，研究成果可分別從感知與推論、生理監測與神經調控、能量取得與有效利用加以敘述。三者以感測器端的晶片與系統設計相互連結：智慧運算降低資料搬移與反應延遲，生醫應用提供具體驗證情境，能源管理則支援感測與運算的持續運作。以下以已完成之電路、論文、專利及合作成果說明，並在各領域交代其後續應用方向。The three areas connect perception and inference, physiological monitoring and neural modulation, and energy acquisition and efficient use. Sensor-side IC and system design links them: intelligent computing reduces data movement and response latency, biomedical applications provide validation settings, and energy management supports continuous sensing and computation. The records below distinguish completed circuits, papers, patents and collaborations from subsequent application directions.
依國立臺灣科技大學核章績效資料，2011年8月1日至2025年7月31日之一般產學合作計畫共24件；2011年8月1日至2024年12月31日之國科會計畫一覽表列20筆。另於2011年8月1日至2025年7月31日之專利一覽表列已領證專利13件；技轉收入明細列12筆。各項紀錄依來源期間分列。期刊論文清單列22篇（含early access論文）。According to the NTUST institution-endorsed performance records cited in the CV, general industry–academia projects from 2011-08-01 to 2025-07-31 numbered 24. The NSTC project table for 2011-08-01 to 2024-12-31 contained 20 entries. The patent table for 2011-08-01 to 2025-07-31 contained 13 issued patents;12 technology-transfer income entries. These figures have separate date ranges and recognition scopes. Technology transfer and industry projects can overlap and are not added as total income. The journal list contains 22 papers, including early-access work.
機器人與智慧控制Robotics and Intelligent Control
本領域著重於智慧系統前端的感知與推論。機器人及自主載具需要持續處理多種感測訊號，並在能源與運算資源有限的情況下即時反應。研究團隊由類比感測介面出發，將神經網路運算移近感測器，發展可編程且可重組的低功耗運算晶片，提供智慧控制系統取得訊息與辨識狀態所需的硬體基礎。This area focuses on perception and inference at the front end of intelligent systems. Robots and autonomous vehicles must process multiple sensor signals continuously and respond promptly with limited energy and computing resources. Building on analog sensing interfaces, the team brings neural computation closer to sensors through programmable, reconfigurable low-power computing ICs, providing hardware for acquiring information and recognizing system states.
類比遞迴神經網路與事件驅動運算Analog Recurrent Neural Networks and Event-Driven Computation
針對連續感測波形先轉為數位資料、再儲存與運算所增加的功耗及延遲，研究團隊將遞迴神經網路的離散運算轉換為連續時間類比電路，結合記憶體內運算直接處理輸入波形。網路權重可儲存於靜態隨機記憶體或嵌入式類比快閃記憶體，並以模組疊接方式擴充至多層網路，使晶片兼具持續感知與可調整運算模型的能力。Digitizing continuous sensor waveforms before storing and processing them adds energy consumption and latency. The team maps discrete recurrent-neural-network operations to continuous-time analog circuits and combines them with in-memory computing to process input waveforms directly. Weights can be stored in SRAM or embedded analog flash memory, and stacked modules extend the architecture to multilayer networks with continuous perception and adjustable models.
研究細節與關鍵結果Research details & key results
此架構可沿用通用軟體工具進行權重訓練，再將權重載入晶片。以Cadence連續時間電路模擬與PyTorch離散時間運算比較，輸出變化的相關係數達94%以上。團隊已完成180 nm製程晶片；在所使用的2,000筆神經脈衝標記資料中，分類正確率達98.5%，並以200筆MIT心電圖資料展示90%以上的分類正確率，運算效能達3.46 TOPS/W。這些結果展示了感測波形直接進行邊緣推論的能力，也為後續導入智慧控制的狀態辨識建立實作基礎。Weights can be trained with standard software tools and then loaded into the IC. Comparisons between Cadence continuous-time circuit simulation and PyTorch discrete-time computation show output correlations above 94%. The team completed 180 nm ICs: classification accuracy reached 98.5% on the 2,000 labeled neural-spike records used in the study and exceeded 90% on 200 MIT ECG records, with computational efficiency of 3.46 TOPS/W. These results demonstrate direct edge inference on sensor waveforms and provide an implementation basis for future state recognition in intelligent control.
在嵌入式類比快閃記憶體實作上，團隊完成5 ms、6位元精度的編程平台，以支援事件驅動感測與類比神經網路。相關邊緣智慧感測晶片獲2026年未來科技獎；類比門控循環單元及其系統實作，亦於2025年及2026年連續兩年榮獲經濟部「智慧創新大賞」學生組IC設計類『銀牌』，並獲媒體專文報導(2025年「臺科大學生打造 AGRU 類比 AI 晶片 穿戴醫療續航力大躍進」報導連結、2026年「走出資料中心PECK 用類比晶片打造 AI與實體世界的互動平臺」報導連結)。這一系列工作串聯了演算法、電路架構、權重編程與晶片驗證。The embedded analog-flash implementation includes a programming platform achieving 6-bit precision in 5 ms for event-driven sensing and analog neural networks. Related edge-sensing ICs received the 2026 Future Tech Award. Analog gated recurrent units and their systems received Silver Medals in the student IC-design category of the MOEA Best AI Awards in 2025 and 2026, with accompanying media coverage. This work connects algorithms, circuit architecture, weight programming and IC validation.
記憶體內認知運算與可重組推論In-Memory Cognitive Computing and Reconfigurable Inference
另一項成果為以靜態隨機記憶體實現可重組認知運算陣列，接受類比或數位輸入，支援帶符號與不帶符號的整數乘加運算，並提供ReLU、RBF及Sigmoid等非線性函數。輸出可串接至其他運算晶片，形成可擴充的神經網路，使同一硬體能依感測任務重新設定，降低為不同應用重新設計晶片的需求。A separate result is a reconfigurable SRAM-based cognitive computation matrix. It accepts analog or digital input, supports signed and unsigned integer multiply–accumulate operations, and provides nonlinear functions including ReLU, RBF and Sigmoid. Its output can connect to other computing ICs to form extensible neural networks, allowing the same hardware to be reconfigured for different sensing tasks.
研究細節與關鍵結果Research details & key results
研究團隊在180 nm製程下設計晶片在4位元乘加運算下達3.6 TOPS/W；配合晶片校正演算法，在10,000筆MNIST手寫數字資料上達95%以上辨識正確率，與軟體運算結果差距小於1個百分點。成果於2024年刊登IEEE Journal of Solid-State Circuits，並於AICAS 2024發表延伸研究。其貢獻在於把記憶、運算與非線性轉換整合於感測器端，為低延遲推論與可調整的智慧感測平台提供電路實現。The 180 nm IC achieved 3.6 TOPS/W for 4-bit multiply–accumulate operations. With calibration, recognition accuracy exceeded 95% on 10,000 MNIST handwritten-digit records, within one percentage point of the software result. The work appeared in IEEE Journal of Solid-State Circuits in 2024, with extensions at AICAS 2024. It integrates memory, computation and nonlinear conversion at the sensor edge for low-latency inference and configurable sensing platforms.
感測介面與智慧控制的應用連結Connecting Sensing Interfaces to Intelligent Control
在感測介面方面，研究團隊與臺大研究團隊合作，利用共振頻率與品質因數量測物質的介電特性，完成非接觸感測電路及系統模組。相關成果取得臺灣與美國專利，於2018年授權工研院，並延伸為鮮度感測原型，獲2019年光寶創新獎技術創新組銀賞。後續LC共振感測研究於2025年刊登Bulletin of the Chemical Society of Japan，獲選Award Article及當期封面，並於2026年發表電解質與液滴之即時非接觸介電感測成果。In sensing interfaces, collaboration with an NTU team uses resonance frequency and quality factor to measure material dielectric properties, producing contactless sensing circuits and system modules. Related Taiwan and US patents were licensed to ITRI in 2018 and extended to a freshness-sensing prototype that received the 2019 Lite-On Award’s Silver Award in technology innovation. Subsequent LC-resonator work appeared in Bulletin of the Chemical Society of Japan in 2025 as an Award Article and issue cover; real-time contactless dielectric sensing of electrolytes and droplets was published in 2026.
研究細節與關鍵結果Research details & key results
上述成果形成由實體量測、訊號處理至即時判讀的技術基礎。面向機器人與智慧控制，後續可將可重組感測介面與類比推論晶片結合，支援環境或物件狀態辨識，並與控制研究團隊合作驗證感知結果如何驅動系統反應。現有實作以感測及推論晶片為主，機器人整機與閉迴路控制的整合則為可進一步發展的應用方向。These results establish a technical foundation from physical measurement through signal processing to real-time interpretation. Future robotics and intelligent-control applications can combine reconfigurable sensing interfaces with analog-inference ICs for environmental or object-state recognition and collaborate with control teams to validate system responses. Current implementations center on sensing and inference ICs; complete robots and closed-loop control integration remain further application directions.
精準智慧醫療Precision Smart Healthcare
本領域以生理訊號品質、長時間監測及神經刺激的可控性為主要研究問題。研究團隊由低功耗生醫感測電路逐步延伸至多通道神經介面、非接觸監測及人工智慧訊號分析，將前端量測、訊號判讀與刺激輸出連結，支援穿戴式、植入式及居家照護相關研究。This area addresses physiological-signal quality, long-term monitoring and controllable neural stimulation. Low-power biomedical sensing circuits have expanded into multichannel neural interfaces, contactless monitoring and AI signal analysis, connecting front-end measurement, interpretation and stimulation output for wearable, implantable and home-care research.
低功耗生醫感測前端Low-Power Biomedical Sensing Front Ends
為兼顧微弱生理訊號的雜訊、線性度與耗能需求，研究團隊利用懸浮閘類比編程及互補式差動架構，發展可重組低雜訊放大器，並以閘極平衡虛擬電阻改善低頻失真。相關電路可調整增益與頻寬；不同設計及操作條件下，展示2.81 μVrms等效輸入雜訊，以及100 Hz頻寬下75 nW的低功耗感測。成果分別於2014年及2015年發表於IEEE Transactions on Biomedical Circuits and Systems與IEEE Transactions on Circuits and Systems II。To balance noise, linearity and energy needs for weak physiological signals, the team uses floating-gate analog programming and complementary differential architectures to develop reconfigurable low-noise amplifiers, with gate-balanced pseudo-resistors improving low-frequency distortion. Gain and bandwidth are adjustable. Different designs and operating conditions demonstrate 2.81μVrms equivalent input noise and 75 nW sensing power at 100 Hz bandwidth. Results appeared in IEEE Transactions on Biomedical Circuits and Systems in 2014 and IEEE Transactions on Circuits and Systems II in 2015.
研究細節與關鍵結果Research details & key results
在濾波與訊號調理上，團隊發展可編程轉導電容濾波器，以線性化轉導架構降低功耗，並透過非揮發性記憶體調整低通或帶通響應及串接級數。二階濾波器在2 kHz頻率條件下達107.2 nW功耗與57.2 dB無雜散動態範圍，並完成高階濾波器整合與量測。相關研究刊登於2018年IEEE Transactions on Circuits and Systems I，後續懸浮閘電晶體電容濾波器研究亦於2023年發表。這些成果使感測前端能依不同生理訊號調整，而不必每次重新設計晶片。Programmable transconductance–capacitor filters use linearized transconductance architectures to reduce power. Nonvolatile memory configures low-pass or band-pass responses and cascaded stages. A second-order filter operating at 2 kHz achieved 107.2 nW and 57.2 dB spurious-free dynamic range, followed by integration and measurement of higher-order filters. Results appeared in IEEE Transactions on Circuits and Systems I in 2018, with floating-gate transistor–capacitor filter work in 2023. The front end can adapt to different physiological signals without a new IC design for each task.
在類比數位轉換上，團隊提出動態鄰近檢測比較器與旁通切換逐次逼近式轉換器，利用生理訊號多數時間變化較小的特性，減少不必要的電容切換。10位元、0.18 μm製程晶片的能量效率指標，在弦波輸入下為3.99 fJ/conversion-step，在心電訊號輸入下為2.66 fJ/conversion-step。成果於2018年刊登IEEE Journal of Solid-State Circuits，並取得相關專利與技術授權，建立由感測、濾波至數位化的低功耗前端技術。For analog-to-digital conversion, the team developed a dynamic proximity-detection comparator and bypass-switching SAR converter. Physiological signals often change slowly, allowing unnecessary capacitor switching to be reduced. A 10-bit IC in 0.18μm technology achieved an energy-efficiency figure of 3.99 fJ/conversion-step for sinusoidal input and 2.66 fJ/conversion-step for ECG input. The work appeared in IEEE Journal of Solid-State Circuits in 2018 and led to patents and licensing, supporting a low-power chain from sensing and filtering to digitization.
自適電流調變與感測系統節能Autonomous Current Adaptation for Sensing Efficiency
團隊發展自適電流調變緩衝放大器，使電路在訊號快速變化時自動增加驅動電流，待輸出穩定後回復低功耗狀態。相關成果刊登IEEE Transactions on Biomedical Circuits and Systems，並獲VLSI Design/CAD 2022之Analog & RF領域Best Paper Award。2023年進一步改善暫態響應，在未增加靜態功耗的條件下，將步階暫態響應時間縮短62.1%、迴轉率提高3.1倍，並降低諧波失真17 dB；成果刊登IEEE Transactions on Circuits and Systems II，並再次獲該研討會Best Paper Award。An autonomous current-adaptation buffer supplies additional drive current when a signal changes quickly and returns to lower power after settling. Related work appeared in IEEE Transactions on Biomedical Circuits and Systems and received the Analog & RF Best Paper Award at VLSI Design/CAD 2022. In 2023, transient-response improvements reduced step-response time by 62.1%, increased slew rate 3.1-fold and reduced harmonic distortion by 17 dB without increasing static power. Results appeared in IEEE Transactions on Circuits and Systems II and again received the symposium’s Best Paper Award.
研究細節與關鍵結果Research details & key results
相同的依需供應電流概念亦延伸至類比數位轉換器輸入驅動電路：取樣瞬間提供較大電流加速穩定，保持相位則回復低電流。於原研究的操作條件下，50%取樣占空比可節省一半以上功耗，10%取樣占空比時可節省76%。成果於2024年刊登IEEE Transactions on Circuits and Systems I。這些電路屬於感測系統用電端的節能技術，可與能源擷取及穩壓電路配合，從能源供應與負載消耗兩端改善整體效能。The same current-on-demand principle extends to ADC input drivers: larger current during sampling accelerates settling, while the hold phase returns to low current. Under the study’s operating conditions, a 50% sampling duty cycle saved more than half the power and a 10% duty cycle saved 76%. The result appeared in IEEE Transactions on Circuits and Systems I in 2024. This load-side energy saving can complement energy-harvesting and regulation circuits to improve system efficiency from both supply and consumption perspectives.
神經訊號擷取與深腦電刺激Neural Recording and Deep-Brain Stimulation
在系統整合上，團隊將低雜訊放大器、濾波器、緩衝放大器及穩壓器整合為四通道類比感測前端，透過類比記憶體及串列介面設定增益、頻寬與訊號路徑。晶片於2020年底與臺大獸醫研究團隊合作進行癲癇動物腦波量測，並於ISCAS 2021發表；後續持續擴展多通道神經感測，相關八通道前端電路於APCCAS 2024發表。The team integrates low-noise amplifiers, filters, buffers and regulators into a four-channel analog sensing front end. Analog memory and serial interfaces configure gain, bandwidth and signal paths. In late 2020, collaboration with an NTU veterinary team measured EEG in epileptic animals; the result was presented at ISCAS 2021. Subsequent multichannel neural-sensing work included an eight-channel front end at APCCAS 2024.
研究細節與關鍵結果Research details & key results
在神經調控方面，研究團隊自2016年參與跨校醫工合作團隊，並於2017年至2019年計畫期間完成可選擇脈衝或指數衰減波形的四通道雙相位電流模式刺激晶片。設計以推挽式電荷補償控制刺激後殘餘電荷，並整合藍牙控制平台與手持裝置介面，完成大鼠及小鼠的癲癇抑制動物實驗。此成果提供可調整刺激參數並控制電荷平衡的電路與實驗平台；動物驗證結果構成後續研究的依據。Since 2016, the professor has participated in an inter-university medical–engineering collaboration. During the 2017–2019 project, the team completed a four-channel biphasic current-mode stimulator supporting pulsed and exponentially decaying waveforms. Push–pull charge compensation controls residual charge after stimulation. Bluetooth control and a handheld interface were integrated, and seizure-suppression animal experiments were conducted in rats and mice. These are circuit-platform and animal-validation results supporting further research.
相關電荷補償技術於2021年取得專利，刺激晶片研究於2023年刊登Integration, the VLSI Journal，並透過與工研院的合作進行技術移轉。共同研究團隊以癲癇預測及封閉式深層腦刺激研究獲2022年第十九屆國家新創獎。這一系列工作使研究團隊之研究由生理訊號量測進一步延伸至可控制的神經刺激，並與智慧判讀技術形成後續閉迴路神經調控研究的基礎。The charge-compensation technology received a patent in 2021. Stimulator-IC work appeared in Integration, the VLSI Journal in 2023, with technology transfer through ITRI collaboration. The joint research team’s seizure prediction and closed-loop deep-brain-stimulation work received the 19 th National Innovation Award in 2022. Together, these results extend physiological measurement into controllable neural stimulation and provide a basis for further closed-loop neuromodulation research with intelligent interpretation.
非接觸感測與人工智慧訊號分析Contactless Sensing and AI Signal Analysis
為降低長時間監測時的配戴負擔，研究團隊與合作團隊建立毫米波雷達生理訊號量測平台，擷取呼吸與心跳引起的胸腔微動，並以跨模態學習重建對應心電波形。相關成果於2024年刊登IEEE Sensors Journal，將非接觸機械運動量測與電生理訊號分析連結，提供智慧照護的研究途徑。此方法的心電波形來自模型重建，其後續應用仍需依使用情境持續驗證。To reduce the burden of wearing sensors during long-term monitoring, the collaboration uses a millimeter-wave radar platform to capture small chest movements caused by breathing and heartbeat, then reconstructs corresponding ECG waveforms with cross-modal learning. The work appeared in IEEE Sensors Journal in 2024. The ECG waveform is reconstructed by a model, and subsequent use still requires validation for the intended setting.
研究細節與關鍵結果Research details & key results
在肌電訊號方面，合作研究利用深度學習去除心電干擾，並以Transformer與U-Net改善表面肌電訊號品質，成果分別於ICASSP 2023及2025年IEEE Journal of Biomedical and Health Informatics發表。這些工作著重於提升訊號可用性，為後續的生理狀態判讀、復健評估及人機介面研究提供較可靠的輸入。For surface EMG, collaborative deep-learning research removes ECG artifacts and uses Transformer and U-Net architectures to improve signal quality. Results appeared at ICASSP 2023 and in IEEE Journal of Biomedical and Health Informatics in 2025. Improving signal usability supplies more reliable input for physiological-state interpretation, rehabilitation assessment and human–machine interfaces.
此外，團隊以低解析度熱影像進行起立行走測試的關鍵點偵測，並延伸至多任務步態分析；相關成果於AICAS 2025及2026年IEEE Sensors Journal發表。結合前述神經、心電與肌電研究，研究團隊在精準智慧醫療領域的貢獻，涵蓋低功耗量測電路、低識別化感測與訊號分析演算法，可進一步與醫療團隊合作，依具體照護需求驗證監測指標與系統效能。Low-resolution thermal imaging supports keypoint detection in the Timed Up-and-Go test and extends to multitask gait analysis, with results at AICAS 2025 and in IEEE Sensors Journal in 2026. Together with neural, ECG and EMG work, these contributions span low-power measurement circuits, sensing with reduced identifiability and signal-analysis algorithms. Further medical collaboration can validate monitoring measures and system performance for specific care needs.
電源管理與綠能Power Management and Green Energy
本領域聚焦微量環境能源的取得、轉換與有效利用。對穿戴式裝置及分散式感測節點而言，持續運作除了仰賴低功耗感測與推論，也需要能在低輸入電壓下啟動、追蹤可用功率並穩定供電的電源管理電路。研究團隊從熱電能量擷取、低靜態電流穩壓及自適電流調變三方面，改善感測系統在有限能源下的運作能力。This area focuses on acquiring, converting and efficiently using small amounts of environmental energy. Wearables and distributed sensing nodes need low-power sensing and inference, along with power-management circuits that start at low voltage, track available power and supply stable energy. The work improves operation under limited energy through thermoelectric harvesting, low-quiescent-current regulation and autonomous current adaptation.
熱電能量擷取與高效率電源轉換Thermoelectric Harvesting and Efficient Power Conversion
團隊發展單電感多輸出熱電能量擷取介面，將冷啟動、最大功率點追蹤與升降壓轉換整合，處理微量熱電能源的啟動與分配問題。2017年於TJCAS發表具280 mV冷啟動能力的相關轉換器，並於ISCAS 2023發表熱電能量擷取系統之冷啟動電路研究。這些成果建立低電壓能源進入感測系統所需的電路基礎。Single-inductor multiple-output thermoelectric interfaces integrate cold start, maximum power point tracking and buck–boost conversion to address startup and allocation of small thermoelectric energy sources. A converter with 280 mV cold-start capability was presented at TJCAS 2017, followed by thermoelectric cold-start circuit work at ISCAS 2023. These results establish circuitry for bringing low-voltage environmental energy into sensing systems.
研究細節與關鍵結果Research details & key results
後續研究進一步發展雙輸入單電感多輸出架構，結合最大功率點追蹤、操作模式切換與能量再利用，提升能源轉換及負載供應的整合程度。相關熱電能量擷取系統獲2024年度優良晶片優等設計獎；整合冷啟動、最大功率點追蹤與能量再利用的介面電路研究，獲VLSI Design/CAD 2025之Analog & RF領域Best Paper Award第一名。此方向以微能量擷取及電源管理晶片為核心，支援自主供能感測節點的發展。Later work develops a dual-input single-inductor multiple-output architecture with maximum power point tracking, operating-mode switching and energy reuse. The thermoelectric system received a 2024 Excellent Chip Design Award. An interface integrating cold start, maximum power point tracking and energy reuse received first place in the Analog & RF Best Paper Award at VLSI Design/CAD 2025. This direction centers on small-energy harvesting and power-management ICs for autonomously powered sensing nodes.
可編程低靜態電流穩壓器Programmable Low-Quiescent-Current Regulators
為避免電源管理電路本身消耗過多能源，團隊開發無須外接輸出電容的可編程低壓差穩壓器，以AB類輸入級在負載變動時提供較大的瞬時調節能力，穩態時則維持低電流。量測展示250 nA靜態電流、200 mV最低壓降與0.17 mV/V電源調整率，在0.1%輸出電壓誤差條件下可供應1 mA負載。To limit the energy consumed by power management itself, the team developed a programmable low-dropout regulator without an external output capacitor. A class-AB input stage provides larger instantaneous regulation during load changes while maintaining low steady-state current. Measurements showed 250 nA quiescent current,200 mV minimum dropout and 0.17 mV/V line regulation, supplying a 1 mA load at 0.1% output-voltage error.
研究細節與關鍵結果Research details & key results
此設計以懸浮閘類比編程調整輸出電壓與頻寬，並利用儲存電荷產生參考電壓，減少額外參考電路的耗能需求。在−20 °C至80 °C操作範圍內，溫度係數低於45 ppm/°C。成果於2017年刊登IEEE Transactions on Circuits and Systems I，並取得相關專利，適合進一步整合於穿戴式、植入式及微能量供電感測平台。Floating-gate analog programming adjusts output voltage and bandwidth, and stored charge generates the reference voltage to reduce the energy required by an additional reference circuit. The temperature coefficient is below 45 ppm/°C over−20°C to 80°C. Results appeared in IEEE Transactions on Circuits and Systems I in 2017 and led to related patents, supporting integration in wearable, implantable and small-energy-powered sensing platforms.
後續研究可將微能量擷取、可編程供電與事件驅動智慧感測整合，依可用能源及感測任務調整運作模式，朝長時間、低維護需求的感測節點發展。這也使電源管理與綠能成果能支援前述機器人感知及智慧醫療應用，形成由能源、感測至運算的跨領域研究基礎。Further work can integrate small-energy harvesting, programmable supply and event-driven sensing, adapting operating modes to available energy and sensing tasks for long-duration, low-maintenance nodes. This connects power-management and green-energy research to robotics perception and smart healthcare, building a cross-domain foundation from energy through sensing to computation.
技術成果探索Explore our technologies
低功耗低延遲低記憶體需求適合感測邊緣應用之類比遞迴神經網路Analog Recurrent Neural Network for Low-Power, Low-Latency, Memory-Efficient Edge Sensing
Our analog recurrent neural network (RNN) IC combines continuous-time signal processing with in-memory computing, eliminating the need to digitize sensor waveforms with an ADC or store them in large digital memories. This removes the bandwidth and power bottlenecks caused by data conversion and movement, enabling low-power, low-latency intelligence directly at the sensing edge.
本技術以創新類比遞迴神經網路積體電路，結合記憶體內運算，省去ADC與大量數位記憶體，實現低功耗低延遲即時智慧運算，相容於現有工具鏈，具高準確率與可擴充性，應用於神經訊號與心電圖分類，展現邊緣AI突破性發展。
完整技術說明Full technical description
隨著生成式大語言模型發展逐漸成熟，智慧無人載具與機器人近年來已成為國內外各大科技公司競逐的新興科技與市場。這些可移動智慧載具接收來自真實世界之訊號與刺激，需要進行低延遲之人工智慧運算以快速做出即時反應，或與人類產生密切互動，預計將成為下一波改變人類日常生活樣貌的關鍵未來科技。根據ABI Research，2025年「邊緣人工智慧晶片組」市場規模將達到122億美元，首度超越雲端AI晶片組的119億美元；SNS Insider預測，全球邊緣AI晶片市場將以年複合成長率高達33.93%之增速，預計到2032年將達到2,215.1億美元規模。近年來機器人及智慧載具所搭載之感測器數目也出現愈來愈多之趨勢，伴隨大幅成長的是由感測器所產生之數位化資料，及對用於暫存資料記憶體容量之需求，因此相對應資料傳輸與運算之頻寬也大幅增加。受限於移動載具所能供應之電源有限，全球科技公司無不全力發展及使用價錢昂貴之新進製程半導體元件、超高頻寬記憶體、及先進異質封裝技術，以降低感測運算系統資料搬移之功耗。研究團隊所開發之創新遞迴神經網路架構及積體電路，省去傳統系統將類比波形取樣後數位化之處理，利用類比訊號處理技術結合記憶體內運算之前瞻創新科技，實現低功耗低延遲之類比資訊直接轉換。由於不再使用類比數位轉換電路進行輸入訊號數位量化，因此也不需要大量數位記憶體儲存感測器訊號，完全避免傳統系統因資訊數位化所造成之頻寬及功耗瓶頸。所開發之遞迴神經網路積體電路可以靜態隨機記憶體或嵌入式類比快閃記憶體做為網路權重之儲存單元，可依不同應用利用通用之數位軟體程式進行神經網路訓練後，再將權重值載入積體電路內之記憶體中。積體電路實現也考慮神經網路之可擴充性，已設計積體電路模組可以疊接方式實現多層之遞迴神經網路。電路模擬軟體Cadence之連續時間輸出值變化與數位軟體PyTorch之離散序列變化之間互相關係數已可達94%以上，因此所研發技術可利用市面上現有軟體工具鏈而不需再開發使用特製神經網路訓練軟體工具，可加速推進邊緣端智慧感測系統應用發展。研究團隊所開發設計之積體電路晶片已可展示使用於即時之神經脈衝波形分類及辨別心臟疾病之心電圖波形分類。研究團隊參與2025年經濟部「智慧創新大賞」榮獲學生組IC設計類『銀牌』。
本技術以創新類比遞迴神經網路積體電路，結合記憶體內運算，省去ADC與大量數位記憶體，實現低功耗低延遲即時智慧運算，相容於現有工具鏈，具高準確率與可擴充性，應用於神經訊號與心電圖分類，展現邊緣AI突破性發展。
An August 2020 ABI Research forecast projected 2025 revenue of US$12.2 billion for edge AI chipsets and US$11.9 billion for cloud AI chipsets. A June 2025 SNS Insider forecast projected an edge AI chips market of US$221.51 billion by 2032 at a 33.93% compound annual growth rate.
Our analog recurrent neural network (RNN) IC combines continuous-time signal processing with in-memory computing, eliminating the need to digitize sensor waveforms with an ADC or store them in large digital memories. This removes the bandwidth and power bottlenecks caused by data conversion and movement, enabling low-power, low-latency intelligence directly at the sensing edge.
The architecture supports weights stored in either SRAM or embedded analog flash memory and can be trained with existing software tools before the weights are programmed into the chip. Its modular design can be cascaded into multilayer RNNs, and Cadence circuit simulations correlate with PyTorch results at more than 94%. Prototype chips have demonstrated real-time neural-spike and ECG classification. The project received the Silver Award in the IC Design Student Category at the 2025 Best AI Awards.
高運算效能之靜態隨機記憶體內認知運算陣列電路設計High-Throughput SRAM In-Memory Cognitive Computing Array
We developed a programmable SRAM in-memory computing array that accepts both real-time analog signals and digital inputs. It supports signed and unsigned integer multiply-accumulate operations and provides ReLU, RBF, and sigmoid activation functions. Current-mode outputs can feed additional chips, allowing larger neural networks to be assembled through chip-level cascading.
近年來智慧物聯網的盛行，傳統類比電路負責提高信噪比，再由類比數位訊號轉換器進行數位化儲存，將人工智慧運算交由數位電路處理。為了減少資料搬移之功耗，許多文獻提出記憶體內運算架構，但通常能夠支援的乘加法格式有限。由於感測器訊號通常以類比形式呈現，若能夠以類比輸入方式直接進行認知運算，將可節省類比數位訊號轉換器及時脈產生器之功耗，並降低運算延遲而能即時認知反應，進而可動態調整感測電路功耗及效能模式，達到系統節能的目的。教授研究團隊創新設計一靜態隨機記憶體內可編程認知運算陣列，不僅可以接受類比即時訊號或是數位數值輸入，並可支援實現帶符號(Signed)及不帶符號(Unsigned)輸入及權重整數乘加法運算。所開發之認知運算陣列輸出電路也提供ReLU、RBF、及Sigmoid三種常見非線性活化函數，輸出之電流也可做為其他認知運算晶片之輸入而得以晶片疊接方式達到實現大型神經網路的目的。研究團隊利用180nm製程所設計之晶片在實現四位元之乘加法運算可達到3.6TOPS/W之效能。若假設所需之能量主要受限於寄生電容而與製程尺寸成平方關係，所設計之電路若以28nm製程可推估運算效能將達148TOPS/W。針對製程變異影響運算準確度，研究團隊提出兩個使用精簡參數進行晶片校正之演算法，並據以利用晶片實現單一層神經網路之運算，在執行10,000筆MNIST手寫數字辨識可達95%以上之正確率，與軟體數值運算正確率相比差距小於1%。初步之研究成果已於2024年2月正式發表於國際頂級固態電子電路期刊IEEE Journal of Solid-State Circuits，相關研究成果也已完成中華民國發明專利申請。此論文之延伸成果也於2024年獲接受國際重要旗艦會議IEEE International Conference on Artificial Intelligence Circuits and Systems (IEEE AICAS 2024)以口頭方式發表。
完整技術說明Full technical description
近年來智慧物聯網的盛行，傳統類比電路負責提高信噪比，再由類比數位訊號轉換器進行數位化儲存，將人工智慧運算交由數位電路處理。為了減少資料搬移之功耗，許多文獻提出記憶體內運算架構，但通常能夠支援的乘加法格式有限。由於感測器訊號通常以類比形式呈現，若能夠以類比輸入方式直接進行認知運算，將可節省類比數位訊號轉換器及時脈產生器之功耗，並降低運算延遲而能即時認知反應，進而可動態調整感測電路功耗及效能模式，達到系統節能的目的。教授研究團隊創新設計一靜態隨機記憶體內可編程認知運算陣列，不僅可以接受類比即時訊號或是數位數值輸入，並可支援實現帶符號(Signed)及不帶符號(Unsigned)輸入及權重整數乘加法運算。所開發之認知運算陣列輸出電路也提供ReLU、RBF、及Sigmoid三種常見非線性活化函數，輸出之電流也可做為其他認知運算晶片之輸入而得以晶片疊接方式達到實現大型神經網路的目的。研究團隊利用180nm製程所設計之晶片在實現四位元之乘加法運算可達到3.6TOPS/W之效能。若假設所需之能量主要受限於寄生電容而與製程尺寸成平方關係，所設計之電路若以28nm製程可推估運算效能將達148TOPS/W。針對製程變異影響運算準確度，研究團隊提出兩個使用精簡參數進行晶片校正之演算法，並據以利用晶片實現單一層神經網路之運算，在執行10,000筆MNIST手寫數字辨識可達95%以上之正確率，與軟體數值運算正確率相比差距小於1%。初步之研究成果已於2024年2月正式發表於國際頂級固態電子電路期刊IEEE Journal of Solid-State Circuits，相關研究成果也已完成中華民國發明專利申請。此論文之延伸成果也於2024年獲接受國際重要旗艦會議IEEE International Conference on Artificial Intelligence Circuits and Systems (IEEE AICAS 2024)以口頭方式發表。
We developed a programmable SRAM in-memory computing array that accepts both real-time analog signals and digital inputs. It supports signed and unsigned integer multiply-accumulate operations and provides ReLU, RBF, and sigmoid activation functions. Current-mode outputs can feed additional chips, allowing larger neural networks to be assembled through chip-level cascading.
Fabricated in a 180 nm process, the four-bit prototype achieves 3.6 TOPS/W; under the assumption that energy is dominated by parasitic capacitance and scales with the square of feature size, a 28 nm implementation is estimated to reach 148 TOPS/W. Two lightweight calibration algorithms compensate for process variation, enabling more than 95% accuracy on 10,000 MNIST images with less than a one-percentage-point gap from software. The work was published in IEEE Journal of Solid-State Circuits in February 2024, and a Taiwan invention patent application was filed. Extended results were presented orally at AICAS 2024 (2024 IEEE 6th International Conference on Artificial Intelligence Circuits and Systems).
自適電流調變緩衝放大器Adaptive Current-Modulation Buffer Amplifier
Conventional output buffers are designed for the highest expected slew rate and therefore waste power during the long periods when biomedical signals change slowly. Our adaptive current-modulation buffer senses rapid input transitions and automatically increases its input-stage current; once the output catches up, feedback reduces the current and restores the low-power operating state.
教授創新設計自適電流調變緩衝放大器電路，當輸入電壓劇烈變化時，輸入電容自動感測並增加輸入級電流以增加放大器電路迴轉率，當輸出電壓追上輸入電壓變化時，迴授電容也會自動感測並降低輸入級電流以回復低功耗穩定狀態。在輸入訊號頻率較低、訊號振幅變化較小時，所設計的放大器電路功耗較小，當輸入訊號頻率升高、振幅變化較大、或負載電容較大時，瞬間功耗可最大自動增加92倍之多，放大器電路自行視輸入訊號變化而快速地動態調整電流大小。教授提出兩個分別用於評比大訊號及小訊號功率效能之修正效能評估指標，在大訊號效能評估指標中加入正規化輸入線性範圍以更公平地比較電路線性度；在小訊號效能評估指標中加入熱電壓項使該指標較不易隨溫度變異而不同。教授所設計緩衝放大器大訊號及小訊號功率效能皆較優於已發表電路，研究成果刊登於頂級生醫電子期刊IEEE Transactions on Biomedical Circuits and Systems，亦獲第33屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2022)之Analog & RF領域『Best Paper Award』。原版設計之緩衝放大器電路於2023年針對暫態響應進行改良優化設計，在不耗費額外靜態功耗的情況下，將步階暫態響應時間縮短62.1%、將電路迴轉率提高3.1倍、並將諧波失真降低17dB，改良成果已於2023年十月獲頂級電路系統期刊IEEE Transactions on Circuits and Systems II: Express Briefs刊登，並再度榮獲第34屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2023)之Analog & RF領域『Best Paper Award』。
完整技術說明Full technical description
緩衝放大器主要用以驅動晶片外負載，以高線性度避免失真為主要設計考量。當輸入訊號有劇烈變化時，放大器電路輸出電壓變化受限於迴轉(slewing)現象，為了保持輸出訊號完整性，緩衝放大器功耗通常會取決於所感測訊號之最大迴轉率。一般生理訊號只在極短暫時間內快速上升或下降，大部份時間訊號變化不大，若能夠只在短暫訊號變化期間增加電流以增加電路迴轉率，而在大部份時間維持較低功耗，將可有效降低系統平均功耗。已知文獻中之可調變電流放大器電路架構通常需要一偵測變化之感測電路及一個動態調變電流之控制電路，感測電路速度太慢將錯失訊號而造成失真，因此勢必要將增加感測電路電流而降低功率效能，因此低功耗緩衝放大器電路是類比電路設計領域長久以來之難題。
教授創新設計自適電流調變緩衝放大器電路，當輸入電壓劇烈變化時，輸入電容自動感測並增加輸入級電流以增加放大器電路迴轉率，當輸出電壓追上輸入電壓變化時，迴授電容也會自動感測並降低輸入級電流以回復低功耗穩定狀態。在輸入訊號頻率較低、訊號振幅變化較小時，所設計的放大器電路功耗較小，當輸入訊號頻率升高、振幅變化較大、或負載電容較大時，瞬間功耗可最大自動增加92倍之多，放大器電路自行視輸入訊號變化而快速地動態調整電流大小。教授提出兩個分別用於評比大訊號及小訊號功率效能之修正效能評估指標，在大訊號效能評估指標中加入正規化輸入線性範圍以更公平地比較電路線性度；在小訊號效能評估指標中加入熱電壓項使該指標較不易隨溫度變異而不同。教授所設計緩衝放大器大訊號及小訊號功率效能皆較優於已發表電路，研究成果刊登於頂級生醫電子期刊IEEE Transactions on Biomedical Circuits and Systems，亦獲第33屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2022)之Analog & RF領域『Best Paper Award』。原版設計之緩衝放大器電路於2023年針對暫態響應進行改良優化設計，在不耗費額外靜態功耗的情況下，將步階暫態響應時間縮短62.1%、將電路迴轉率提高3.1倍、並將諧波失真降低17dB，改良成果已於2023年十月獲頂級電路系統期刊IEEE Transactions on Circuits and Systems II: Express Briefs刊登，並再度榮獲第34屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2023)之Analog & RF領域『Best Paper Award』。
Conventional output buffers are designed for the highest expected slew rate and therefore waste power during the long periods when biomedical signals change slowly. Our adaptive current-modulation buffer senses rapid input transitions and automatically increases its input-stage current; once the output catches up, feedback reduces the current and restores the low-power operating state.
Depending on signal frequency, amplitude, and load capacitance, instantaneous power consumption can increase to as much as 92 times the baseline. The design outperforms prior work under revised large- and small-signal power-efficiency metrics. The large-signal metric includes normalized input linear range, while the small-signal metric includes thermal voltage to reduce temperature dependence. It received the Analog & RF Best Paper Awards at VLSI Design/CAD 2022 and 2023. Related results were published in IEEE Transactions on Biomedical Circuits and Systems and IEEE Transactions on Circuits and Systems II: Express Briefs. The 2023 transient-response enhancement reduced step-response time by 62.1%, increased slew rate by a factor of 3.1, and reduced harmonic distortion by 17 dB without additional static power; the enhancement was published in October 2023.
自適電流調變輸入驅動電路Adaptive Current-Modulation ADC Input Driver
ADC input drivers can consume more than ten times the power of the converter itself because they must settle within a very short sampling interval. Our driver detects the input-output transition at the sampling instant and temporarily supplies a large current for rapid settling, then automatically returns to a low-current mode during the hold phase.
除了緩衝放大器電路之外，教授也創新開發自適電流調變之類比數位轉換輸入驅動電路，一般來說輸入驅動電路之功耗可較類比數位轉換電路本身大上十倍以上，但是探討此電路之文獻卻遠少於類比數位轉換電路。所消耗之功耗主要是要滿足在極短的取樣時間內使驅動電路之輸出達到穩定平衡的狀態，因此驅動電路通常消耗大電流以滿足極大之迴轉率。教授所創新提出之驅動電路能夠自動感應取樣瞬間輸入與輸出端之變化而產生大電流使輸出電壓快速達到穩定平衡狀態，之後的保持相位期間便可自動回復到低電流模式達到省電的目的。所提出之自適電流調變驅動電路在50%的時脈週期下可較傳統電路架構節省一半以上的功耗，在高速類比數位轉換需求下，時脈週期有可能減少至10%時，所創新提出之驅動電路更可節省76%之功耗。此研究成果已於2024年八月正式發表於國際頂級電路與系統期刊IEEE Transactions on Circuits and Systems I: Regular Papers。
完整技術說明Full technical description
除了緩衝放大器電路之外，教授也創新開發自適電流調變之類比數位轉換輸入驅動電路，一般來說輸入驅動電路之功耗可較類比數位轉換電路本身大上十倍以上，但是探討此電路之文獻卻遠少於類比數位轉換電路。所消耗之功耗主要是要滿足在極短的取樣時間內使驅動電路之輸出達到穩定平衡的狀態，因此驅動電路通常消耗大電流以滿足極大之迴轉率。教授所創新提出之驅動電路能夠自動感應取樣瞬間輸入與輸出端之變化而產生大電流使輸出電壓快速達到穩定平衡狀態，之後的保持相位期間便可自動回復到低電流模式達到省電的目的。所提出之自適電流調變驅動電路在50%的時脈週期下可較傳統電路架構節省一半以上的功耗，在高速類比數位轉換需求下，時脈週期有可能減少至10%時，所創新提出之驅動電路更可節省76%之功耗。此研究成果已於2024年八月正式發表於國際頂級電路與系統期刊IEEE Transactions on Circuits and Systems I: Regular Papers。
ADC input drivers can consume more than ten times the power of the converter itself because they must settle within a very short sampling interval. Our driver detects the input-output transition at the sampling instant and temporarily supplies a large current for rapid settling, then automatically returns to a low-current mode during the hold phase.
At a 50% clock duty cycle, the proposed architecture reduces power by more than half compared with conventional drivers. At a 10% sampling duty cycle, representative of high-speed conversion, the saving reaches 76%. The work was published in IEEE Transactions on Circuits and Systems I: Regular Papers in August 2024.
動態鄰近檢測比較器之低功耗類比數位轉換電路設計Low-Power ADC with a Dynamic Proximity-Detection Comparator
Biomedical signals often remain within a narrow amplitude range. Detecting this condition early allows a successive-approximation ADC to bypass unnecessary binary-search steps and avoid switching large capacitors. We created a dynamic proximity-detection comparator that determines both signal polarity and whether the absolute input lies inside a preset bypass window during a single comparison phase.
教授研究團隊創新提出一新穎之動態鄰近檢測比較器電路，可在同一比較相位產生輸入訊號之正負極性並判斷輸入訊號之絕對值是否落在預設旁通窗內，可大幅節省電路晶片面積，並節省額外比較器或粗略轉換器之功耗，且所設計類比數位轉換電路之數位邏輯電路可再減化，進而節省更多的功耗。另外所設計之旁通窗大小對參考電壓之靈敏度大幅減少120倍，使得此參考電壓之產生電路也可以整合進晶片中，因此為類比混訊積體電路設計領域之一大突破，非常適合需要低功耗之生醫感測應用。所設計之10位元類比數位轉換器晶片利用0.18 µm製程，量測正弦波輸入時，所得之FoM可達3.99 fJ/ Conversion-step，而當電路晶片用來量測心電訊號時，所得之FoM可降低到2.66 fJ/Conversion-step，功率效能大幅度地提高。此研究成果已於2018年6月刊登於世界頂級固態電路期刊IEEE Journal of Solid-State Circuits，所申請之中華民國及美國發明專利均已獲核准通過，中華民國發明專利於2022年完成非專屬專利技術授權。
完整技術說明Full technical description
許多類比數位轉換電路中需要比較器電路進行輸入訊號與參考電壓之比較，再視結果依序切換不同位元之電容陣列以進行二元搜尋數位化程序。由於生醫訊號在長時間振幅不大，若能夠提早偵測訊號振幅大小是否落於所設定之旁通窗內，將可減少所需二元搜尋之步驟，進而有效減少較大電容切換次數及功耗。為了實現此旁通窗之偵測電路，有許多文獻提出使用三個比較器及兩個高精確度之參考電壓，或是使用另一個粗略類比數位轉換電路進行預先轉換，其代價都將增加電路實現之複雜度、晶片使用面積、及伴隨而來的額外功耗。
教授研究團隊創新提出一新穎之動態鄰近檢測比較器電路，可在同一比較相位產生輸入訊號之正負極性並判斷輸入訊號之絕對值是否落在預設旁通窗內，可大幅節省電路晶片面積，並節省額外比較器或粗略轉換器之功耗，且所設計類比數位轉換電路之數位邏輯電路可再減化，進而節省更多的功耗。另外所設計之旁通窗大小對參考電壓之靈敏度大幅減少120倍，使得此參考電壓之產生電路也可以整合進晶片中，因此為類比混訊積體電路設計領域之一大突破，非常適合需要低功耗之生醫感測應用。所設計之10位元類比數位轉換器晶片利用0.18 µm製程，量測正弦波輸入時，所得之FoM可達3.99 fJ/ Conversion-step，而當電路晶片用來量測心電訊號時，所得之FoM可降低到2.66 fJ/Conversion-step，功率效能大幅度地提高。此研究成果已於2018年6月刊登於世界頂級固態電路期刊IEEE Journal of Solid-State Circuits，所申請之中華民國及美國發明專利均已獲核准通過，中華民國發明專利於2022年完成非專屬專利技術授權。
Biomedical signals often remain within a narrow amplitude range. Detecting this condition early allows a successive-approximation ADC to bypass unnecessary binary-search steps and avoid switching large capacitors. We created a dynamic proximity-detection comparator that determines both signal polarity and whether the absolute input lies inside a preset bypass window during a single comparison phase.
The circuit avoids extra comparators or a coarse converter, reduces area and digital logic, and makes the bypass window 120 times less sensitive to its reference voltage. A 10-bit 0.18 µm prototype achieves 3.99 fJ/conversion-step for sinusoidal inputs and 2.66 fJ/conversion-step for ECG signals. The work appeared in IEEE Journal of Solid-State Circuits in June 2018. Its Taiwan and US invention patents have been granted, and the Taiwan patent was licensed non-exclusively in 2022.
可編程重組低功耗類比濾波器積體電路設計Programmable Reconfigurable Low-Power Analog Filter IC
Low-frequency biomedical filtering demands very large passive components when conventional closed-loop op-amp structures are used. We instead employ an open-loop OTA-C architecture and linearize the transconductor through optimized multiple differential pairs and nonlinearity cancellation. The optimized multiple-differential-pair OTA reduces power consumption to 15% of that of a conventional differential pair. A complementary-differential-pair OTA extends the linear input range by more than tenfold compared with a conventional OTA at the same bandwidth.
教授也提出一個新的評量指標線性效能因數比較不同線性化技巧所衍生之運算轉導放大器電路架構。所提出之線性效能因數並不隨電路偏壓不同而改變，也不受電容性輸入衰減技巧影響評估值，因此可以公平地評斷不同電路架構於線性化、頻寬、功耗間進行取捨之效能表現。此研究成果於2018年發表於積體電路與系統期刊IEEE Transactions on Circuits and Systems I: Regular Papers，並獲核准兩項中華民國發明專利及兩項美國發明專利。
完整技術說明Full technical description
在各式不同的感測應用中，在放大器電路後及類比數位轉換電路前通常會有一類比濾波器電路濾掉干擾與雜訊，或消除數位取樣後所產生的混疊頻率訊號。在常見的通訊系統中，由於載波頻率較高，可使用運算放大器以電阻電容網路回授方式設計高線性度之濾波器。而在生醫感測系統中，由於生理訊號頻率低於20kHz，以傳統方式設計濾波器所需要使用之電阻電容值極大，且使用回授放大器的功耗較高，因此需要尋求其他方式設計生醫感測濾波器電路。且為了增加使用彈性，若能夠在晶片製作完成後，以編程方式調整濾波器參數，將可使晶片適用於不同生理訊號之感測需求，而不需重新進行晶片設計與下線。
教授選定運算轉導放大器-電容濾波器架構，由於使用開迴路運作方式，濾波器主動電路之功耗可大幅降低，並可透過調整電流方式改變濾波器參數，然而此架構之線性度取決於運算轉導放大器電路之輸入線性範圍。在極低功耗之生醫感測應用情境中，電晶體將偏壓於次臨界區，使一般差動對電路之線性範圍只受溫度影響，不似操作於強反轉區時可靠增加過驅動電壓而增加。因此在極低功耗下增加運算轉導放大器電路線性範圍其實長久來就是非常具挑戰性之類比電路設計難題。教授利用多擴散器多差動對之電路架構，利用最佳化演算法計算電晶體尺寸來設計運算轉導放大器，利用非線性相消之原理，設計一線性化之轉導運算放大器電路，功耗大幅減少為原本傳統差動對電路之15%。而利用互補式差動對架構合成之運算轉導放大器電路與傳統運算轉導放大器電路相比，在相同頻寬的條件下，可將線性範圍增加超過10倍以上。教授也據以發展低功耗高動態範圍可編程之轉導電容類比二階濾波器電路，並可串接多個二階濾波器實現所需要之高階濾波器頻率響應。所利用四個所提出之運算轉導放大器電路及兩個電容的二階濾波器電路中，可在107.2nW的功耗下實現2kHz的輸出帶通或低通頻率響應，並可達到57.2dB的無雜散動態範圍(SFDR)。電路中也包含一個內含非揮發性記憶體之串列傳輸介面電路，可利用編程非揮發性記憶體方式調整濾波器之輸出選擇及串接級數，此串列傳輸介面電路已獲中華民國及美國之發明專利。若使用常用之濾波器電路綜合評估指標，所提出之濾波器電路表現為目前已知文獻中最佳。論文中除了完整的電路雜訊分析外，也以串接方式實現四階Chebyshev低通濾波及八階Butterworth帶通濾波響應，並量測其功耗、頻率響應、輸入三階截取點、輸入雜訊及無雜散動態範圍。由於此論文對於生醫應用之低頻濾波器電路設計提供完整的解決方案，由最基礎之電晶體次臨界區模型出發，利用非線性相消方式實現創新之差動對電路元件，並進而完成二階濾波器電路模組，並利用模組化電路實現高階濾波響應。理論基礎完備且晶片量測結果完整，量測後之電路性能遠優於目前文獻上所發表之濾波器電路。雖然類比濾波器電路設計已被研發數十年，此論文所提出之電路除了在學理上具創新性外，在線性與功耗效能、晶片面積、可編程性、可擴充性等各方面皆具備實務上之優越性。
教授也提出一個新的評量指標線性效能因數比較不同線性化技巧所衍生之運算轉導放大器電路架構。所提出之線性效能因數並不隨電路偏壓不同而改變，也不受電容性輸入衰減技巧影響評估值，因此可以公平地評斷不同電路架構於線性化、頻寬、功耗間進行取捨之效能表現。此研究成果於2018年發表於積體電路與系統期刊IEEE Transactions on Circuits and Systems I: Regular Papers，並獲核准兩項中華民國發明專利及兩項美國發明專利。
Low-frequency biomedical filtering demands very large passive components when conventional closed-loop op-amp structures are used. We instead employ an open-loop OTA-C architecture and linearize the transconductor through optimized multiple differential pairs and nonlinearity cancellation. The optimized multiple-differential-pair OTA reduces power consumption to 15% of that of a conventional differential pair. A complementary-differential-pair OTA extends the linear input range by more than tenfold compared with a conventional OTA at the same bandwidth.
A programmable second-order filter operates at 2 kHz with 107.2 nW power and 57.2 dB SFDR. Multiple sections were cascaded to demonstrate a fourth-order Chebyshev low-pass response and an eighth-order Butterworth band-pass response, while an on-chip serial interface with non-volatile memory controls the response and cascade configuration. A proposed linearity figure of merit compares tradeoffs among linearity, bandwidth and power; it is independent of bias and unaffected by capacitive input attenuation under the stated evaluation. The work was published in IEEE Transactions on Circuits and Systems I: Regular Papers in 2018 and has received two Taiwan and two US invention patents.
低功耗低雜訊感測放大器積體電路設計Low-Power, Low-Noise Sensing Amplifier IC
Our programmable low-noise sensing amplifier combines floating-gate transistors with complementary differential pairs, simplifying the bias circuitry and approaching the physical limit of noise efficiency. Its theoretical noise-efficiency factor is 1.45 and the measured value is as low as 1.88. A gate-balanced pseudo-resistor also improves low-frequency distortion by more than 20 dB without additional power.
教授於台科大首次使用懸浮閘電晶體，利用互補式差動對之架構，創新提出可編程重組低雜訊感測放大器，可簡化電路架構並減少偏壓電路之功耗，所提出之電路架構之雜訊效能因數理論極限值為1.45，較之前麻省理工Prof. R. Sarpeshkar教授所提之極限值2.02明顯降低，已等同於單一電晶體操作於次臨界區時所得之雜訊效能因數，實為物理之極限，量測所得之雜訊效能因數可低至1.88，為目前所知文獻中之最有效率之低雜訊放大器。除雜訊效能外，教授也針對電容回授放大器因非線性回授電阻所造成低頻失真問題，提出一閘極平衡虛擬電阻電路架構，在不消耗額外功耗的情況下，訊號失真的程度可以改善多達20dB以上。教授所發展之低功耗低雜訊放大器量測所得之等效輸入雜訊為2.81μVrms，在10Hz輸入訊號下，量測所得之訊號動態範圍可達62dB以上，總諧波失真可減少至0.1%，放大器感測頻率範圍可連續調整，低頻高通轉角頻率最小可至50mHz，高頻低通轉角頻率可達20kHz，在100Hz頻寬的感測應用中，只需消耗75nW之功耗。由於此放大器具有可編程重組、高動態範圍、低雜訊、低功耗之特性，適合對功耗要求非常嚴苛之穿戴或植入式生醫感測或物聯網之感測器等應用。相關研究已分別於2014及2015年發表在國際期刊IEEE Transactions on Biomedical Circuits and Systems及IEEE Transactions on Circuits and Systems II: Express Briefs，美國及中華民國發明專利均獲核准通過。
完整技術說明Full technical description
教授於台科大首次使用懸浮閘電晶體，利用互補式差動對之架構，創新提出可編程重組低雜訊感測放大器，可簡化電路架構並減少偏壓電路之功耗，所提出之電路架構之雜訊效能因數理論極限值為1.45，較之前麻省理工Prof. R. Sarpeshkar教授所提之極限值2.02明顯降低，已等同於單一電晶體操作於次臨界區時所得之雜訊效能因數，實為物理之極限，量測所得之雜訊效能因數可低至1.88，為目前所知文獻中之最有效率之低雜訊放大器。除雜訊效能外，教授也針對電容回授放大器因非線性回授電阻所造成低頻失真問題，提出一閘極平衡虛擬電阻電路架構，在不消耗額外功耗的情況下，訊號失真的程度可以改善多達20dB以上。教授所發展之低功耗低雜訊放大器量測所得之等效輸入雜訊為2.81μVrms，在10Hz輸入訊號下，量測所得之訊號動態範圍可達62dB以上，總諧波失真可減少至0.1%，放大器感測頻率範圍可連續調整，低頻高通轉角頻率最小可至50mHz，高頻低通轉角頻率可達20kHz，在100Hz頻寬的感測應用中，只需消耗75nW之功耗。由於此放大器具有可編程重組、高動態範圍、低雜訊、低功耗之特性，適合對功耗要求非常嚴苛之穿戴或植入式生醫感測或物聯網之感測器等應用。相關研究已分別於2014及2015年發表在國際期刊IEEE Transactions on Biomedical Circuits and Systems及IEEE Transactions on Circuits and Systems II: Express Briefs，美國及中華民國發明專利均獲核准通過。
Our programmable low-noise sensing amplifier combines floating-gate transistors with complementary differential pairs, simplifying the bias circuitry and approaching the physical limit of noise efficiency. Its theoretical noise-efficiency factor is 1.45 and the measured value is as low as 1.88. A gate-balanced pseudo-resistor also improves low-frequency distortion by more than 20 dB without additional power.
The amplifier achieves 2.81 µVrms input-referred noise, more than 62 dB dynamic range at 10 Hz, and 0.1% total harmonic distortion. Its passband can be continuously programmed from a 50 mHz high-pass corner to a 20 kHz low-pass corner, while a 100 Hz-bandwidth configuration consumes only 75 nW. The design is suitable for wearable, implantable, and IoT sensing and has been published in IEEE TBioCAS and IEEE TCAS-II, with Taiwan and US patents granted.
低功耗高效能之可編程線性穩壓電路設計Low-Power, High-Performance Programmable Linear Regulator
We developed an ultra-low-power, capacitor-free linear regulator for sensor front ends whose total power budgets are below 10 µW. A class-AB error amplifier raises its current only during output transitions, accelerating recovery while preserving very low quiescent power in steady state.
傳統線性穩壓電路都是設計給負載電流約在數百毫安培的應用系統中，因此穩壓電路本身的功耗並不特別受到重視，通常都在數十微瓦左右。在IoT時代所設計之感測前端電路之功耗已經在十微瓦以內，因此必須設計功耗在一微瓦以下之超低功耗線性穩壓電路，提供穩定而精確的電壓給負載電流較小之類比前端電路系統；同時為了減小感測系統的體積，穩壓器電路應該要在無外加電容的情況下皆能穩定，這樣的規格其實極為困難。教授研究團隊設計了一個可編程重組且無須外加電容之超低功耗穩壓器電路，其中使用一個含AB類輸入級之誤差放大器，只有在輸出電壓變動時，放大器的電流才會增加，以加速調節輸出電壓回復至穩定值，而在靜態時電流可以很小以達到節省功耗的目的。量測所得之最低壓降(dropout voltage)為200mV，靜態電流為250nA，量測所得之電源調整率為0.17mV/V，在0.1%的輸出電壓誤差下，最大負載電流為1mA。由於所設計之線性穩壓電路使用懸浮閘類比編程技術，穩壓器電路之輸出電壓及頻寬皆可視不同應用需求而連續地調整。此外，此線性穩壓器電路利用儲存於懸浮閘的電荷產生一參考電壓，因此不需要使用額外之能隙參考電路，而可節省多餘的功耗。當所設計之電路操作在-20°C至80°C之間時，量測所得之溫度係數小於45ppm/°C，適合於大多數之應用。雖然所設計之穩壓器電路不需外加電容，但當負載電容增加至1nF時，穩壓器電路仍可保持穩定。由於所設計超低功耗穩壓器電路具可調整輸出電壓及頻寬之特性，且其電源調整率極佳，此電路將除可應用於穿戴式及植入式生醫感測系統中外，也可適用於許多能量來源極少的無線感測的環境中。所創新研發之穩壓電路在靜態功耗、暫態響應、電源抗干擾能力、參考電壓產生方式、可編程性、及使用方便性等方面皆具學理上之創新性及實務上之優越性。研究成果已於2017年刊登於積體電路與系統之頂級期刊IEEE Transactions on Circuits and Systems I: Regular Papers，也獲得中華民國發明專利。
完整技術說明Full technical description
傳統線性穩壓電路都是設計給負載電流約在數百毫安培的應用系統中，因此穩壓電路本身的功耗並不特別受到重視，通常都在數十微瓦左右。在IoT時代所設計之感測前端電路之功耗已經在十微瓦以內，因此必須設計功耗在一微瓦以下之超低功耗線性穩壓電路，提供穩定而精確的電壓給負載電流較小之類比前端電路系統；同時為了減小感測系統的體積，穩壓器電路應該要在無外加電容的情況下皆能穩定，這樣的規格其實極為困難。教授研究團隊設計了一個可編程重組且無須外加電容之超低功耗穩壓器電路，其中使用一個含AB類輸入級之誤差放大器，只有在輸出電壓變動時，放大器的電流才會增加，以加速調節輸出電壓回復至穩定值，而在靜態時電流可以很小以達到節省功耗的目的。量測所得之最低壓降(dropout voltage)為200mV，靜態電流為250nA，量測所得之電源調整率為0.17mV/V，在0.1%的輸出電壓誤差下，最大負載電流為1mA。由於所設計之線性穩壓電路使用懸浮閘類比編程技術，穩壓器電路之輸出電壓及頻寬皆可視不同應用需求而連續地調整。此外，此線性穩壓器電路利用儲存於懸浮閘的電荷產生一參考電壓，因此不需要使用額外之能隙參考電路，而可節省多餘的功耗。當所設計之電路操作在-20°C至80°C之間時，量測所得之溫度係數小於45ppm/°C，適合於大多數之應用。雖然所設計之穩壓器電路不需外加電容，但當負載電容增加至1nF時，穩壓器電路仍可保持穩定。由於所設計超低功耗穩壓器電路具可調整輸出電壓及頻寬之特性，且其電源調整率極佳，此電路將除可應用於穿戴式及植入式生醫感測系統中外，也可適用於許多能量來源極少的無線感測的環境中。所創新研發之穩壓電路在靜態功耗、暫態響應、電源抗干擾能力、參考電壓產生方式、可編程性、及使用方便性等方面皆具學理上之創新性及實務上之優越性。研究成果已於2017年刊登於積體電路與系統之頂級期刊IEEE Transactions on Circuits and Systems I: Regular Papers，也獲得中華民國發明專利。
We developed an ultra-low-power, capacitor-free linear regulator for sensor front ends whose total power budgets are below 10 µW. A class-AB error amplifier raises its current only during output transitions, accelerating recovery while preserving very low quiescent power in steady state.
Measurements show a 200 mV dropout voltage, 250 nA quiescent current, 0.17 mV/V line regulation, and up to 1 mA load current at 0.1% output error. Floating-gate analog programming provides continuous control of output voltage and bandwidth and eliminates a separate bandgap reference. The measured temperature coefficient remains below 45 ppm/°C from −20°C to 80°C. The regulator remains stable with load capacitance up to 1 nF despite requiring no external capacitor. The work was published in IEEE Transactions on Circuits and Systems I: Regular Papers and received a Taiwan invention patent.
多通道類比感測前端系統晶片Multi-Channel Analog Sensing Front-End SoC
Our four-channel sensing front-end SoC integrates a low-noise amplifier, two second-order filters, differential-to-single-ended buffers, and a low-quiescent-current regulator in each channel. Floating-gate devices serve as non-volatile analog memory, allowing parameters such as bandwidth, output level, and quality factor to be programmed after fabrication.
教授先逐一開發創新之低功耗類比感測前端中包含感測放大器、濾波器、穩壓器、緩衝放大器、類比數位轉換器等子電路，同時進行電路整合以發展四通道之感測前端系統晶片，每個類比感測通道包含一個低雜訊放大器、兩個二階線性濾波器、及兩個雙端轉單端之緩衝放大器以提供單端或雙端之類比電壓輸出、以及一個低靜態電流之穩壓器。每個電路內皆包含數個至十幾個懸浮閘電晶體做為非揮發性類比記憶體，而可以電荷編程方式調整如頻寬、輸出電壓位準、品質因數等電路參數。其中非揮發性類比記憶體編程所需之部份電路也整合於系統晶片中。晶片內也包含一個具有非揮發性記憶體之串列傳輸介面電路，可以數位離散方式選擇放大器增益、濾波器低通或帶通響應輸出、緩衝放大器輸出模式、各子電路啟用連接或關閉旁通等選項，使晶片在製作完成後可以依據不同的使用情境與需求調整類比感測前端電路的特性，且晶片一旦完成記憶體編程後，往後使用時不需要再以晶片外之微處理器進行電源啟動設定步驟，而能夠讓使用者隨插即用。所設計的四通道類比感測晶片於2020年底於所合作之臺大獸醫學院張芳嘉教授實驗室進行動物實驗量測癲癇老鼠之腦波訊號。初步研究成果於2021年以國際研討會議論文形式，以線上會議口頭報告預錄形式發表於電路系統領域之旗艦會議IEEE International Symposium on Circuits and Systems (ISCAS 2021)，並於會議中口頭回覆與會者之提問。後續之多通道類比感測前端系統晶片之研發目前仍在繼續進行中，預計將於2022年將類比數位轉換電路及高效能之類比記憶體編程電路一併整合至系統晶片中。
完整技術說明Full technical description
教授先逐一開發創新之低功耗類比感測前端中包含感測放大器、濾波器、穩壓器、緩衝放大器、類比數位轉換器等子電路，同時進行電路整合以發展四通道之感測前端系統晶片，每個類比感測通道包含一個低雜訊放大器、兩個二階線性濾波器、及兩個雙端轉單端之緩衝放大器以提供單端或雙端之類比電壓輸出、以及一個低靜態電流之穩壓器。每個電路內皆包含數個至十幾個懸浮閘電晶體做為非揮發性類比記憶體，而可以電荷編程方式調整如頻寬、輸出電壓位準、品質因數等電路參數。其中非揮發性類比記憶體編程所需之部份電路也整合於系統晶片中。晶片內也包含一個具有非揮發性記憶體之串列傳輸介面電路，可以數位離散方式選擇放大器增益、濾波器低通或帶通響應輸出、緩衝放大器輸出模式、各子電路啟用連接或關閉旁通等選項，使晶片在製作完成後可以依據不同的使用情境與需求調整類比感測前端電路的特性，且晶片一旦完成記憶體編程後，往後使用時不需要再以晶片外之微處理器進行電源啟動設定步驟，而能夠讓使用者隨插即用。所設計的四通道類比感測晶片於2020年底於所合作之臺大獸醫學院張芳嘉教授實驗室進行動物實驗量測癲癇老鼠之腦波訊號。初步研究成果於2021年以國際研討會議論文形式，以線上會議口頭報告預錄形式發表於電路系統領域之旗艦會議IEEE International Symposium on Circuits and Systems (ISCAS 2021)，並於會議中口頭回覆與會者之提問。後續之多通道類比感測前端系統晶片之研發目前仍在繼續進行中，預計將於2022年將類比數位轉換電路及高效能之類比記憶體編程電路一併整合至系統晶片中。
Our four-channel sensing front-end SoC integrates a low-noise amplifier, two second-order filters, differential-to-single-ended buffers, and a low-quiescent-current regulator in each channel. Floating-gate devices serve as non-volatile analog memory, allowing parameters such as bandwidth, output level, and quality factor to be programmed after fabrication.
An on-chip serial interface with non-volatile memory controls gain, filter response, buffer mode, and block bypass options. Once programmed, the chip powers up without requiring an external processor, enabling plug-and-play operation. The prototype recorded EEG signals from rats with epilepsy in animal experiments conducted at National Taiwan University in late 2020. Initial results were presented through a prerecorded online talk at IEEE ISCAS 2021, followed by responses to audience questions.
多通道深腦電刺激系統晶片Multi-Channel Deep-Brain Stimulation SoC
Since 2016, we have collaborated with a multidisciplinary team to develop a closed-loop deep-brain stimulation system for epilepsy. The resulting SoC contains a modular, programmable four-channel biphasic current stimulator with selectable pulse or exponentially decaying waveforms and a novel push-pull charge-compensation circuit.
教授於2016年起參加由臺大醫院劉宏輝副院長帶領，由臺大電子所呂學士教授、林宗賢教授、楊家驤教授、臺大獸醫學院張芳嘉教授、交大電機所闕河鳴教授所組成之癲癇預測深腦電刺激系統晶片開發之研究團隊，並自2017年至2019年獲科技部補助研究計畫研發應用於深層腦刺激之電刺激器積體電路。教授於計畫期間完成可選擇脈衝或指數衰減波形之模組化可編程四通道雙相位電流模式電刺激系統晶片設計、量測與效能驗證，並創新設計一推挽式電荷補償電路，於2021年7月獲證中華民國發明專利。此外也完成所設計之電刺激晶片藍芽模組控制平台及手持式裝置上使用者介面程式，並利用此控制平台及所開發之晶片分別以大鼠及小鼠完成電刺激抑制癲癇發作之動物實驗，且驗證電刺激晶片所提供之電刺激並不會對腦部組織產生傷害，並可有效抑制癲癇大發作之產生。研究成果論文於2023年獲SCI國際期刊Integration, the VLSI Journal刊登。所開發之電刺激控制平台與晶片曾於2020年及2021年以產學合作案方式技術移轉至工研院協助產業推廣。教授及共同研究團隊也於2022年以「難治型癲癇症治療新策略: 預測癲癇並運用封閉式深層腦刺激術」榮獲第十九屆國家新創獎－臨床新創獎。
完整技術說明Full technical description
教授於2016年起參加由臺大醫院劉宏輝副院長帶領，由臺大電子所呂學士教授、林宗賢教授、楊家驤教授、臺大獸醫學院張芳嘉教授、交大電機所闕河鳴教授所組成之癲癇預測深腦電刺激系統晶片開發之研究團隊，並自2017年至2019年獲科技部補助研究計畫研發應用於深層腦刺激之電刺激器積體電路。教授於計畫期間完成可選擇脈衝或指數衰減波形之模組化可編程四通道雙相位電流模式電刺激系統晶片設計、量測與效能驗證，並創新設計一推挽式電荷補償電路，於2021年7月獲證中華民國發明專利。此外也完成所設計之電刺激晶片藍芽模組控制平台及手持式裝置上使用者介面程式，並利用此控制平台及所開發之晶片分別以大鼠及小鼠完成電刺激抑制癲癇發作之動物實驗，且驗證電刺激晶片所提供之電刺激並不會對腦部組織產生傷害，並可有效抑制癲癇大發作之產生。研究成果論文於2023年獲SCI國際期刊Integration, the VLSI Journal刊登。所開發之電刺激控制平台與晶片曾於2020年及2021年以產學合作案方式技術移轉至工研院協助產業推廣。教授及共同研究團隊也於2022年以「難治型癲癇症治療新策略: 預測癲癇並運用封閉式深層腦刺激術」榮獲第十九屆國家新創獎－臨床新創獎。
Since 2016, we have collaborated with a multidisciplinary team to develop a closed-loop deep-brain stimulation system for epilepsy. The resulting SoC contains a modular, programmable four-channel biphasic current stimulator with selectable pulse or exponentially decaying waveforms and a novel push-pull charge-compensation circuit.
A Bluetooth control platform and handheld user interface were developed alongside the chip. Rat and mouse studies demonstrated effective seizure suppression without detectable tissue damage. The work was published in Integration, the VLSI Journal in 2023, and the charge-compensation circuit received a Taiwan invention patent in July 2021. Development was supported by Ministry of Science and Technology (MOST) grants from 2017 to 2019. The stimulation platform and chip were transferred to the Industrial Technology Research Institute (ITRI) through industry collaborations in 2020 and 2021. The collaborative project also won the Clinical Innovation Award at the 19th National Innovation Award in 2022.
非接觸之介電係數感測電路與系統模組設計Contactless Permittivity Sensing Circuit and System Module
In collaboration with NTU's Institute of Biomedical Engineering, we developed sensing chips and system modules for contactless material-quality assessment. An antenna serves as the sensor, while our interface circuit extracts resonant frequency and quality factor to determine the material's permittivity.
教授自2012年起與臺大醫工所林啟萬教授合作，開發用以檢測物質品質之感測晶片與系統模組。其中使用林啟萬教授研究團隊所開發之天線作為感測器，教授研究團隊開發其介面電路，利用共振頻率與品質因數來判定待測物之介電係數。相關研究成果於教授任助理教授期間便申請並獲證中華民國發明專利，美國專利則是於教授升等副教授生效後，2016年8月23日公告獲證。初期研究成果也於2017年5月至美國之電路系統領域之旗艦會議IEEE International Symposium on Circuits and Systems (ISCAS 2017)以口頭方式發表。相關技術及專利也於2018年授權並技術移轉至工業技術研究院進行後續產業推廣工作，教授也因此兼任工研院顧問約一年時間，協助相關技術之推廣。期間工研院團隊利用此技術設計一鮮度計之雛形品，由教授擔任指導老師，參加2019年光寶創新獎，榮獲技術創新組之銀賞。後續相關之研究發展仍在積極進行中。
完整技術說明Full technical description
教授自2012年起與臺大醫工所林啟萬教授合作，開發用以檢測物質品質之感測晶片與系統模組。其中使用林啟萬教授研究團隊所開發之天線作為感測器，教授研究團隊開發其介面電路，利用共振頻率與品質因數來判定待測物之介電係數。相關研究成果於教授任助理教授期間便申請並獲證中華民國發明專利，美國專利則是於教授升等副教授生效後，2016年8月23日公告獲證。初期研究成果也於2017年5月至美國之電路系統領域之旗艦會議IEEE International Symposium on Circuits and Systems (ISCAS 2017)以口頭方式發表。相關技術及專利也於2018年授權並技術移轉至工業技術研究院進行後續產業推廣工作，教授也因此兼任工研院顧問約一年時間，協助相關技術之推廣。期間工研院團隊利用此技術設計一鮮度計之雛形品，由教授擔任指導老師，參加2019年光寶創新獎，榮獲技術創新組之銀賞。後續相關之研究發展仍在積極進行中。
In collaboration with NTU's Institute of Biomedical Engineering, we developed sensing chips and system modules for contactless material-quality assessment. An antenna serves as the sensor, while our interface circuit extracts resonant frequency and quality factor to determine the material's permittivity.
The collaboration began in 2012. The technology received Taiwan and US invention patents, with the US patent granted on August 23, 2016, and was presented orally at IEEE ISCAS in the United States in May 2017. It was licensed and transferred to the Industrial Technology Research Institute (ITRI) in 2018 for industrial development. Professor Peng also served as an ITRI consultant for approximately one year to support technology promotion. An ITRI prototype freshness meter based on the technology received the Silver Award in the Technology Innovation Category at the 2019 LITEON Award.