AiSMART Lab 國立陽明交通大學 電機工程研究所Institute of Electrical and Computer Engineering, NYCU

類比人工智慧與神經網路Analog AI and neural networks

機器人與智慧控制Robotics and Intelligent Control

針對連續感測波形先轉為數位資料、再儲存與運算所增加的功耗及延遲，研究團隊將遞迴神經網路的離散運算轉換為連續時間類比電路，結合記憶體內運算直接處理輸入波形。網路權重可儲存於靜態隨機記憶體或嵌入式類比快閃記憶體，並以模組疊接方式擴充至多層網路，使晶片兼具持續感知與可調整運算模型的能力。Digitizing continuous sensor waveforms before storing and processing them adds energy consumption and latency. The team maps discrete recurrent-neural-network operations to continuous-time analog circuits and combines them with in-memory computing to process input waveforms directly. Weights can be stored in SRAM or embedded analog flash memory, and stacked modules extend the architecture to multilayer networks with continuous perception and adjustable models.

另一項成果為以靜態隨機記憶體實現可重組認知運算陣列，接受類比或數位輸入，支援帶符號與不帶符號的整數乘加運算，並提供ReLU、RBF及Sigmoid等非線性函數。輸出可串接至其他運算晶片，形成可擴充的神經網路，使同一硬體能依感測任務重新設定，降低為不同應用重新設計晶片的需求。A separate result is a reconfigurable SRAM-based cognitive computation matrix. It accepts analog or digital input, supports signed and unsigned integer multiply–accumulate operations, and provides nonlinear functions including ReLU, RBF and Sigmoid. Its output can connect to other computing ICs to form extensible neural networks, allowing the same hardware to be reconfigured for different sensing tasks.

原始研究說明：Research descriptions: 技術說明Technology description

相關公開論文Related public papers

依公開論文題名關鍵字篩選，共 8 篇，依公開年份與已載月份由新到舊排列；未載月份者置於該年最後。8 papers matched by title keywords, ordered by published year and stated month, newest first. Entries without a month follow dated entries in the same year.

  1. Towards Bio‑Inspired Edge Intelligence: Precise Analog‑Flash Programming for Reconfigurable Event‑Driven Circuits and Analog Gated Recurrent Units

    Extended Abstracts of the 2026 International Conference on Solid State Devices and Materials, Nagasaki, Japan, 2026. (Invited Speaker)

  2. An Ultra-Low-Power Synthesizable Asynchronous AER Encoder for Neuromorphic Edge Devices

    2026 IEEE 69th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 46-50, Cincinnati, OH, USA, 2026

  3. The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices

    in Proc. 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), pp. 467-471, Abu Dhabi, UAE, April 22~25, 2024. (EI)

  4. An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications

    IEEE Journal of Solid-State Circuits, vol. 59, no. 2, pp. 636-648, Feb. 2024.

  5. A Programmable Analog Radial-Basis-Function Based Classifier

    in Proc. 2008 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Mar. 2008, pp. 1425–1428.

  6. Analog VLSI Implementation of Support Vector Machine Learning and Classification

    in 2008 IEEE International Symposium on Circuits and Systems, pp. 860-863, Seattle, WA, 2008. (EI)

  7. An Analog Programmable Multi-Dimensional Radial Basis Function Based Classifier

    in Proc. 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2007, pp. 13–18.

  8. An Analog Programmable Multidimensional Radial Basis Function Based Classifier

    IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, no.10, pp.2148-2158, 2007.

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