AiSMART Lab 國立陽明交通大學 電機工程研究所Institute of Electrical and Computer Engineering, NYCU

資料轉換器Data converters

精準智慧醫療Precision Smart Healthcare

除了緩衝放大器電路之外，教授也創新開發自適電流調變之類比數位轉換輸入驅動電路，一般來說輸入驅動電路之功耗可較類比數位轉換電路本身大上十倍以上，但是探討此電路之文獻卻遠少於類比數位轉換電路。所消耗之功耗主要是要滿足在極短的取樣時間內使驅動電路之輸出達到穩定平衡的狀態，因此驅動電路通常消耗大電流以滿足極大之迴轉率。教授所創新提出之驅動電路能夠自動感應取樣瞬間輸入與輸出端之變化而產生大電流使輸出電壓快速達到穩定平衡狀態，之後的保持相位期間便可自動回復到低電流模式達到省電的目的。所提出之自適電流調變驅動電路在50%的時脈週期下可較傳統電路架構節省一半以上的功耗，在高速類比數位轉換需求下，時脈週期有可能減少至10%時，所創新提出之驅動電路更可節省76%之功耗。此研究成果已於2024年八月正式發表於國際頂級電路與系統期刊IEEE Transactions on Circuits and Systems I: Regular Papers。ADC input drivers can consume more than ten times the power of the converter itself because they must settle within a very short sampling interval. Our driver detects the input-output transition at the sampling instant and temporarily supplies a large current for rapid settling, then automatically returns to a low-current mode during the hold phase.

教授研究團隊創新提出一新穎之動態鄰近檢測比較器電路，可在同一比較相位產生輸入訊號之正負極性並判斷輸入訊號之絕對值是否落在預設旁通窗內，可大幅節省電路晶片面積，並節省額外比較器或粗略轉換器之功耗，且所設計類比數位轉換電路之數位邏輯電路可再減化，進而節省更多的功耗。另外所設計之旁通窗大小對參考電壓之靈敏度大幅減少120倍，使得此參考電壓之產生電路也可以整合進晶片中，因此為類比混訊積體電路設計領域之一大突破，非常適合需要低功耗之生醫感測應用。所設計之10位元類比數位轉換器晶片利用0.18 µm製程，量測正弦波輸入時，所得之FoM可達3.99 fJ/ Conversion-step，而當電路晶片用來量測心電訊號時，所得之FoM可降低到2.66 fJ/Conversion-step，功率效能大幅度地提高。此研究成果已於2018年6月刊登於世界頂級固態電路期刊IEEE Journal of Solid-State Circuits，所申請之中華民國及美國發明專利均已獲核准通過，中華民國發明專利於2022年完成非專屬專利技術授權。Biomedical signals often remain within a narrow amplitude range. Detecting this condition early allows a successive-approximation ADC to bypass unnecessary binary-search steps and avoid switching large capacitors. We created a dynamic proximity-detection comparator that determines both signal polarity and whether the absolute input lies inside a preset bypass window during a single comparison phase.

教授創新設計自適電流調變緩衝放大器電路，當輸入電壓劇烈變化時，輸入電容自動感測並增加輸入級電流以增加放大器電路迴轉率，當輸出電壓追上輸入電壓變化時，迴授電容也會自動感測並降低輸入級電流以回復低功耗穩定狀態。在輸入訊號頻率較低、訊號振幅變化較小時，所設計的放大器電路功耗較小，當輸入訊號頻率升高、振幅變化較大、或負載電容較大時，瞬間功耗可最大自動增加92倍之多，放大器電路自行視輸入訊號變化而快速地動態調整電流大小。教授提出兩個分別用於評比大訊號及小訊號功率效能之修正效能評估指標，在大訊號效能評估指標中加入正規化輸入線性範圍以更公平地比較電路線性度；在小訊號效能評估指標中加入熱電壓項使該指標較不易隨溫度變異而不同。教授所設計緩衝放大器大訊號及小訊號功率效能皆較優於已發表電路，研究成果刊登於頂級生醫電子期刊IEEE Transactions on Biomedical Circuits and Systems，亦獲第33屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2022)之Analog & RF領域『Best Paper Award』。原版設計之緩衝放大器電路於2023年針對暫態響應進行改良優化設計，在不耗費額外靜態功耗的情況下，將步階暫態響應時間縮短62.1%、將電路迴轉率提高3.1倍、並將諧波失真降低17dB，改良成果已於2023年十月獲頂級電路系統期刊IEEE Transactions on Circuits and Systems II: Express Briefs刊登，並再度榮獲第34屆超大型積體電路設計暨計算機輔助設計技術研討會(VLSI Design/CAD 2023)之Analog & RF領域『Best Paper Award』。Conventional output buffers are designed for the highest expected slew rate and therefore waste power during the long periods when biomedical signals change slowly. Our adaptive current-modulation buffer senses rapid input transitions and automatically increases its input-stage current; once the output catches up, feedback reduces the current and restores the low-power operating state.

原始研究說明：Research descriptions: 技術說明Technology description · 技術說明Technology description · 技術說明Technology description

相關公開論文Related public papers

依公開論文題名關鍵字篩選，共 10 篇，依公開年份與已載月份由新到舊排列；未載月份者置於該年最後。10 papers matched by title keywords, ordered by published year and stated month, newest first. Entries without a month follow dated entries in the same year.

  1. An Asynchronous Delta Modulator for Spike Encoding in Event-Driven Brain-Machine Interface

    2026 IEEE 69th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 110-114, Cincinnati, OH, USA, 2026. (EI)

  2. A Power-Efficient Autonomous Current Adaptation ADC Input Driver

    IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no.8, pp. 3476-3488, Aug. 2024.

  3. A transient-enhanced autonomous current adaptation buffer amplifier

    IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3727-3731, Oct. 2023.

  4. A Reconfigurable Differential-to-Single-Ended Autonomous Current Adaptation Buffer Amplifier Suitable for Biomedical Applications

    IEEE Transactions on Biomedical Circuits and Systems, vol. 15, no. 6, pp. 1405 - 1418, Dec. 2021.

  5. A Calibration Method for Bypass-Switching SAR ADC by Using Self-Capacitor Array

    2019 IEEE International Conference on Analog VLSI Circuits (AVIC 2019), Yilan, Taiwan, Oct. 28~30, 2019.

  6. A Bypass-Switching SAR ADC With a Dynamic Proximity Comparator for Biomedical Applications

    IEEE Journal of Solid-State Circuits, vol. 53, no. 6, pp. 1743-1754, June 2018.

  7. A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

    in Analog Integrated Circuits and Signal Processing, vol. 94, no 1, pp. 65-74, Jan. 2018.

  8. An 85 dB SNDR Third-Order ΔΣ Modulator for Audio Applications

    2017 IEEE/SICE International Symposium on System Integration (SII), pp. 505-510, Taipei, Taiwan, December 11~14, 2017. (EI)

  9. A Bypass-Switching SAR ADC with A Floating-Gate Dual-Core Comparator for Biomedical Application

    2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS 2017), Okayama, Japan, August 21~23, 2017.

  10. Power Efficient Highly Linear Class-AB Input/Output Buffer Amplifier with High Slew Rate

    2017 Taiwan and Japan Conference on Circuits and Systems (TJCAS 2017), Okayama, Japan, August 21~23, 2017.

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